Search On Demand
Recommended Reading
Integrated Power and System Management
In this episode of Chalk TalkHD Amelia chats with Shyam Chandra of Lattice Semiconductor about an integrated approach to system and power management that will lighten your design load, improve your overall system design, and probably lower your total cost at the same time.
Chalk Talk sponsored by Lattice
Using FPGAs for Trapezoidal Motor Control
Whether the need is for quieter blower fans in air conditioning systems, or greater efficiency under dynamically changing load conditions for an electric car drive-train, performance and cost goals for permanent magnet synchronous motor (PMSM or BLDC) controllers become more challenging by the day.
White Paper sponsored by Microsemi
Maximize Design Productivity With PCIe/104 FPGA/Processor
In this episode of Chalk TalkHD Amelia chats with Christine Van De Graaf of Kontron, who explain how Kontron is incorporating pre-made, small form factor boards, a high-performance embedded processor programmable logic into their new MSMST board and how we can get started designing with one.
Chalk Talk sponsored by Kontron
IP and Process Solutions for Energy-efficient PMICs
In this episode of Chalk TalkHD Amelia chats with Ravi Mahatme from ARM and King Ou from GLOBALFOUNDRIES about how IP and process solutions can help solve our power management problems.
Chalk Talk sponsored by ARM
Troubleshooting and Fast Fault Isolation with VTOS
Troubleshooting and quickly isolating faults is of tremendous value for reducing the time to redesign or repair failing boards. This process can cost a company millions of dollars each year. Supporting OMAP, Sitara, QorIQ, PowerQUICC and PowerPC, this paper describes how using an interpreter that allows the execution of a full test suite for verifying a design or an individual test for fault isolation can dramatically improve quality and reliability with Kozio’s Verification and Test OS (VTOS™). It describes how memory errors can be isolated to ECC (Error Control Coding), single-bit, row, column, and correlated to a part’s reference designator.
Sponsored by: Kozio
Implementing FPGA Design with the OpenCL Standard
Utilizing the Khronos Group’s OpenCL™ standard on an FPGA may offer significantly higher performance and at much lower power than is available today from hardware architectures such as CPUs, graphics processing units (GPUs), and digital signal processing (DSP) units. In addition, an FPGA-based heterogeneous system (CPU + FPGA) using the OpenCL standard has a significant time-to-market advantage compared to traditional FPGA development using lower level hardware description languages (HDLs) such as Verilog or VHDL.
White Paper sponsored by Altera
Design Made Easy With the SmartFusion Customizable System-on-Chip and State of the Art Software Tools
Since the early years of embedded processor design and FPGA design, silicon advancement and design techniques for each have evolved independently. In the real world there are many FPGA designs without embedded processors and many embedded systems that neither have nor need an FPGA. This leads to two very distinct design flows, styles, and engineering disciplines. The relatively recent addition of SmartFusion® customizable system-on-chip (cSoC) devices adds the complexity of analog into the mix.
White Paper sponsored by Microsemi
Integrating High-Level Synthesis Designs into SoCs with Less Effort and Risk
High-Level Synthesis (HLS) has many benefits for integrated circuit design but also introduces challenges for integration into SoCs. This paper proposes solutions that improve HLS system integration by eliminating manual interface specification, reducing debug and allow system integration and verification tasks to be performed earlier. By enabling an HLS to SoC flow from a model-based design environment, these methods increase productivity and eliminate manual effort, errors and risk.
White Paper sponsored by Synopsys
Leveraging OCP for Cache Coherent Traffic Within an Embedded Multi-core Cluster
Scaling processing performance beyond the frequency and power envelope of single core systems has led to the emergence of multi-core clusters. Data access management within such processing systems becomes essential to ensure behavioral consistency. One solution to provide access consistency is the application of a memory coherence model such as MESI or MOESI within the L1 data cache hierarchy. For the MIPS Technologies MIPS32® 1004K™ Coherent Processing System (CPS), we applied Open Core Protocol (OCP) point-to-point connectivity to establish snoop-based coherence throughout the cluster. Following are principles of this communication model.
White Paper sponsored by MIPS
High-Reliability in FPGA Design - SEU Mitigation
Neutrons are coming for you and you'd better be prepared. Whether we like it or not, SEUs (Single Event Upsets) are becoming a bigger and bigger problem for our designs, especially for high realibility systems. If you thought SEUs couldn't mess up your next design because you aren't designing something destined for space, you need to think again. In this episode of Chalk TalkHD, I chat with Jeff Garrison of Synopsys about the how we can battle SEUs (on the ground or in the air) with the latest generation of design tools.
Chalk Talk sponsored by Synopsys
chalk talks
Spartan-6 FPGAs in Video Designs
In this episode of Chalk TalkHD, Amelia chats with Tom Hill and Maureen Smerdon of Xilinx about how Spartan-6 FPGAs can accelerate your next video design, and how adding embedded vision to those designs is getting easier and easier.
Chalk Talk sponsored by Xilinx
Scalable Smart Debugging With ZeBu-Server
In this episode of Chalk TalkHD, Amelia chats with Lauro Rizzatti of EVE about how EVE's ZeBu emulation technology can help you find that one last bug in even the biggest of designs.
Chalk Talk sponsored by EvE
Hierarchical Design Flows: Design Preservation & Team Design
In this episode of Chalk TalkHD, Amelia chats with David Dye of Xilinx about how Hierarchical Design methodologies and Team Design can accelerate your next FPGA design and get those team members of yours working productively together. With these tools and techniques, two million logic elements won't seem like that much after all.
Chalk Talk sponsored by Xilinx
Adding Wi-Fi to Your FPGA Design
In the first episode of our new Chalk TalkHD series, Amelia Dalton talks to Bob Potock from Altium as they add Wi-Fi to an FPGA-based embedded system.
Chalk Talk sponsored by Altium
Intel Atom™ Processor with built-in Altera Arria® FPGA
In this Chalk TalkHD Amelia talks to David Schmidt of Arrow about the new Intel Atom™ processor with an Altera Arria FPGA built right into the package.
Chalk Talk sponsored by Arrow
IP and Process Solutions for Energy-efficient PMICs
In this episode of Chalk TalkHD Amelia chats with Ravi Mahatme from ARM and King Ou from GLOBALFOUNDRIES about how IP and process solutions can help solve our power management problems.
Chalk Talk sponsored by ARM
latest papers and content
Integrating High-Level Synthesis Designs into SoCs with Less Effort and Risk
High-Level Synthesis (HLS) has many benefits for integrated circuit design but also introduces challenges for integration into SoCs. This paper proposes solutions that improve HLS system integration by eliminating manual interface specification, reducing debug and allow system integration and verification tasks to be performed earlier. By enabling an HLS to SoC flow from a model-based design environment, these methods increase productivity and eliminate manual effort, errors and risk.
White Paper sponsored by Synopsys
Methods and Tools for Bring-Up and Debug of an FPGA-Based ASIC Prototype
Software simulation of RTL is no longer capable of providing all of the verification required for today's complex ASIC designs. Modern ASICs are a complex mixture of hardware and software, so it is necessary to verify the design within the context of the complete system, running the full range of software at speeds that approach real-time. Successfully validating an ASIC design on an FPGA-based prototype before committing to silicon is now a key project milestone for most design teams. This paper examines some of the best practices for both successful bring-up and logic debug of ASICs using FPGA-based prototypes.
White Paper sponsored by Synopsys
FPGA Prototyping with the Kintex-7 KC705 Evaluation Kit
In this episode of Chalk Talk HD, Amelia chats with Evan Leal of Xilinx about their new Kintex-7 KC705 Evaluation Kit, all the cool stuff that’s included and how we can use it to speed up our FPGA Prototyping.
Chalk Talk sponsored by Xilinx
It's 2022: Do You Know What Your FPGA Is?
Does the definition of "FPGA" seem like a moving target? Over the past few years, there has been phenomenal progress in FPGA technology - going from simple glue logic to impressive programmable systems-on-chip. Today's FPGAs are some of the most powerful and flexible devices ever built. But, what will your FPGA look like ten years from now? In this episode of Chalk TalkHD, Amelia Dalton chats with Umar Mughal of Altera about the past, present, and future of this exciting technology.
Chalk Talk sponsored by Altera
Is Your Memory Design Correct and Reliable?
Learn how quickly and easily you can run a comprehensive memory test and uncover design and reliability issues. In this video, a memory failure is detected only in "burst" mode, while passing all other tests. A second development board passes all the tests.
Embedded Design Verification Best Practices Short Video
Watch this short video on Embedded Design Verification Best Practices and learn how to verify embedded designs for correctness and reliability utilizing a NEW approach employing a Verification and Test OS (VTOS™).
Troubleshooting and Fast Fault Isolation with VTOS
Troubleshooting and quickly isolating faults is of tremendous value for reducing the time to redesign or repair failing boards. This process can cost a company millions of dollars each year. Supporting OMAP, Sitara, QorIQ, PowerQUICC and PowerPC, this paper describes how using an interpreter that allows the execution of a full test suite for verifying a design or an individual test for fault isolation can dramatically improve quality and reliability with Kozio’s Verification and Test OS (VTOS™). It describes how memory errors can be isolated to ECC (Error Control Coding), single-bit, row, column, and correlated to a part’s reference designator.
Sponsored by: Kozio
A Platform for Reducing Verification Time and Improving Reliability of Embedded System Hardware
In this whitepaper the author reviews how leveraging VTOS during the prototype phase can assist engineers in overcoming the challenges design complexity exerts on product development, manufacturing, and overall time-to-market. Readers will gain insight into how they can replace today’s ad-hoc board level verification approaches with an ordered methodology that enables designers to automatically validate their own hardware designs, optimize system performance, and simplify the process of integrating new hardware with new software.
White Paper sponsored by Kozio
Memory Testing 101 – Avoid the Train Wreck
Memory is fundamental to the “sanity” of an embedded system. Inadequate memory testing is posing critical challenges to designers and indirectly manifesting considerable consequences at some of the biggest names in the electronics business. Today’s embedded systems consist of multiple memory types including SDRAM, LPDDR2, DDR3, FLASH, EEPROM and more, along with multiple protocols including GPIO, PCI, SPI and I2C. This paper will review a comprehensive and flexible Verification and Test Operating System (VTOS™) solution that includes a suite of memory tests that verifies the design for correctness and production readiness.
White Paper sponsored by Kozio
Customer Private Label Program
Customers have prototyped their products utilizing Microsemi FPGA & cSoCs and then quickly went to production on the same platform. This ensures design consistency and gets product to their customers on time as scheduled. Microsemi’s private label program goes a step further and provides the ability to custom mark devices with company logo’s and part numbers. Furthermore, our devices do not require an external EEPROM for boot-up configuration, thus the end product can be sold as single IC solution. This approach provides numerous levels of security including prevention of reverse engineering coupled with 128-bit encryption keys to unlock and reprogram your device for field upgradability when the need arises.
New To On Demand?
Registered users can access hundreds of whitepapers, demos, videos, webcasts and more. Sign up now.
Already a registered user? Log in here to access content.
subscribe to journal on demand weekly newsletter
more on demand
FPGA Design Flow and Development Tools
Learn about the Actel tools that are available for creating your FPGA design, whether it be for the ultra low power IGLOO®, high performance ProASIC®3, mixed signal Fusion, or Actel's new SmartFusion™ intelligent mixed signal flash FPGA with hard embedded ARM® Cortex™-M3 microcontroller subsystem.
Understanding Metastability in FPGAs
Metastability is a phenomenon that can cause system failure in digital devices when a signal is transferred between circuitry in unrelated or asynchronous clock domains. This paper describes metastability in FPGAs, explains why the phenomenon occurs, and discusses how it causes design failures. The MTBF due to metastability indicates whether steps should be taken to reduce the chance of such failures. This paper explains how MTBF is calculated, and how both vendors and designers can increase it.
White Paper sponsored by Altera
Enable High-Performance DSP with Variable-Precision DSP Blocks
DSP designs use hundreds or thousands of multipliers as basic building blocks to implement filters, fast Fourier transforms (FFTs), and encoders that digitally process signals. This document highlights the benefits of variable-precision DSP architecture in Altera’s new Arria® V and Cyclone® V FPGAs. Altera's variable precision DSP block allows designers to tailor the precision on a block-by-block basis, thereby saving resources and power while increasing performance.
White Paper sponsored by Altera
Arria V FPGA Sneak Peek: Transceiver Operation at 6.325 Gbps and 10.3125 Gbps
When you want it all, Arria® V devices provide the balance of cost and performance while delivering the lowest total power. Watch this exciting hardware demonstration of the Arria V FPGA's transceiver running at 6.375 Gbps and 10.3125 Gbps.
Generating Panoramic Views by Stitching Multiple Fisheye Images
This white paper discusses an innovative architecture developed by Altera and Manipal Dot Net to generate panoramic views by stitching multiple fisheye images on an FPGA. This architecture provides a complete view of a vehicle’s surroundings to the driver and makes it easier to control and navigate the vehicle.s.
White Paper sponsored by Altera
Compiling, Installing, and Running MIPS NDK Native Applications
Are you working on Android apps development? This app note on the MIPS NDK describes how to build Android applications in native C or C++.
Automotive Top Ten: Ten Points to Consider When Using Logic in Your Next Automotive Design
Automotive electronics designers have been turning more frequently to programmable logic solutions to meet the needs of their next generation designs. FPGAs offer time-to-market benefits along with simplified qualification and greater flexibility in comparison to historic ASIC-based solutions.
White Paper sponsored by Microsemi
Easily Support WDR CMOS Image Sensor Processing with Low-Cost FPGAs
High-definition (HD) wide dynamic range (WDR) CMOS image sensors are ideal for applications like video surveillance cameras. And for the underlying technology, FPGAs are optimal because they deliver the high bandwidth these sensors demand. In this 7-minute video, you'll see how an FPGA-based platform easily performs complex image processing to support WDR CMOS image sensors.